The present invention relates to the implantation of fluorine directly into the channel region of a PMOS transistor structure to improve the 1/f noise and VT drift margin of the device performance.
Mixed signal integrated circuits find the option of dual (or more) gate oxide processes attractive in that multiple voltages can then be used on the same chip. This technique requires that gate oxides be grown twice, to result in different gate oxide thicknesses, and often with different well implantations, so as to provide optimal performance for both the high voltage and the low voltage transistors.
Hook et al., xe2x80x9cThe Effects of Flourine on Parametrics and Reliability in a 0.18xcexcm 3.5/6.8 nm Dual Gate Oxide CMOS Technologyxe2x80x9d, IEEE Transactions on Electron Devices, Vol. 48, No. 7, July 2001, pp. 1346-1353, discuss the benefits of the introduction of fluorine into gate oxide by implantation into the gate polysilicon in PMOS devices.
For reasons of mask count reduction, and thus cost, it is attractive to make use of common source-drain implants, spacer formation and silicidation processing, which are common to both high and low voltage transistors.